/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2018 NXP
 *
 * Register definitions for NXP Flex Serial Peripheral Interface (FSPI)
 */

#ifndef _NXP_FSPI_H_
#define _NXP_FSPI_H_

struct nxp_fspi_regs {
	u32 mcr0;		/* 0h */
	u32 mcr1;
	u32 mcr2;
	u32 ahbcr;
	u32 inten;
	u32 intr;
	u32 lutkey;
	u32 lutcr;
	u32 ahbrxbuf0cr0;
	u32 ahbrxbuf1cr0;
	u32 ahbrxbuf2cr0;
	u32 ahbrxbuf3cr0;
	u32 ahbrxbuf4cr0;	/* 30h */
	u32 ahbrxbuf5cr0;
	u32 ahbrxbuf6cr0;
	u32 ahbrxbuf7cr0;
	u32 ahbrxbuf0cr1;
	u32 ahbrxbuf1cr1;
	u32 ahbrxbuf2cr1;
	u32 ahbrxbuf3cr1;
	u32 ahbrxbuf4cr1;
	u32 ahbrxbuf5cr1;
	u32 ahbrxbuf6cr1;
	u32 ahbrxbuf7cr1;
	u32 flsha1cr0;		/* 60h */
	u32 flsha2cr0;
	u32 flshb1cr0;
	u32 flshb2cr0;
	u32 flsha1cr1;
	u32 flsha2cr1;
	u32 flshb1cr1;
	u32 flshb2cr1;
	u32 flsha1cr2;
	u32 flsha2cr2;
	u32 flshb1cr2;
	u32 flshb2cr2;
	u32 flshcr3;		/* 90h */
	u32 flshcr4;
	u32 flshcr5;
	u32 flshcr6;
	u32 ipcr0;
	u32 ipcr1;
	u32 ipcr2;
	u32 ipcr3;
	u32 ipcmd;
	u32 dlpr;
	u32 iprxfcr;
	u32 iptxfcr;
	u32 dllacr;		/* C0h */
	u32 dllbcr;
	u32 misccr2;
	u32 misccr3;
	u32 misccr4;
	u32 misccr5;
	u32 misccr6;
	u32 misccr7;
	u32 sts0;		/* E0h */
	u32 sts1;
	u32 sts2;
	u32 ahbspndsts;
	u32 iprxfsts;
	u32 iptxfsts;
	u32 rsvd[2];
	u32 rfdr[32];		/* 100h */
	u32 tfdr[32];
	u32 lut[128];
};

/* The registers */
/* Module Control Register 0 */
#define FSPI_MCR0_AHBGRANTWAIT_SHIFT	24
#define FSPI_MCR0_AHBGRANTWAIT_MASK	(0xFF << FSPI_MCR0_AHBGRANTWAIT_SHIFT)
#define FSPI_MCR0_IPGRANTWAIT_SHIFT	16
#define FSPI_MCR0_IPGRANTWAIT_MASK	(0xFF << FSPI_MCR0_IPGRANTWAIT_SHIFT)
#define FSPI_MCR0_LEARNEN_SHIFT		15
#define FSPI_MCR0_LEARNEN_MASK		(1 << FSPI_MCR0_LEARNEN_SHIFT)
#define FSPI_MCR0_SCKFREERUNEN_SHIFT	14
#define FSPI_MCR0_SCKFREERUNEN_MASK	(1 << FSPI_MCR0_SCKFREERUNEN_SHIFT)
#define FSPI_MCR0_COMBINATIONEN_SHIFT	13
#define FSPI_MCR0_COMBINATION_MASK	(1 << FSPI_MCR0_COMBINATION_SHIFT)
#define FSPI_MCR0_DOZEEN_SHIFT		12
#define FSPI_MCR0_DOZEEN_MASK		(1 << FSPI_MCR0_DOZEEN_SHIFT)
#define FSPI_MCR0_HSEN_SHIFT		11
#define FSPI_MCR0_HSEN_MASK		(1 << FSPI_HSEN_SHIFT)
#define FSPI_MCR0_SERCLKDIV_SHIFT	8
#define FSPI_MCR0_SERCLKDIV_MASK	(7 << FSPI_MCR0_SERCLKDIV_SHIFT)
#define FSPI_MCR0_ATDFEN_SHIFT		7
#define FSPI_MCR0_ATDFEN_MASK		(1 << FSPI_MCR0_ATDFEN_SHIFT)
#define FSPI_MCR0_ARDFEN_SHIFT		6
#define FSPI_MCR0_ARDFEN_MASK		(1 << FSPI_MCR0_ARDFEN_SHIFT)
#define FSPI_MCR0_RXCLKSRC_SHIFT	4
#define FSPI_MCR0_RXCLKSRC_MASK		(3 << FSPI_MCR0_RXCLKSRC_SHIFT)
#define FSPI_MCR0_ENDCFG_SHIFT		2
#define FSPI_MCR0_ENDCFG_MASK		(3 << FSPI_MCR0_ENDCFG_SHIFT)
#define FSPI_MCR0_MDIS_SHIFT		1
#define FSPI_MCR0_MDIS_MASK		(1 << FSPI_MCR0_MDIS_SHIFT)
#define FSPI_MCR0_SWRESET_SHIFT		0
#define FSPI_MCR0_SWRESET_MASK		(1 << FSPI_MCR0_SWRESET_SHIFT)

/* Module Control Register 1 */
#define FSPI_MCR1_SEQWAIT_SHIFT		16
#define FSPI_MCR1_SEQWAIT_MASK		(0xFFFF << FSPI_MCR1_SEQWAIT_SHIFT)
#define FSPI_MCR1_AHBBUSWAIT_SHIFT	0
#define FSPI_MCR1_AHBBUSWAIT_MASK	(0xFFFF << FSPI_MCR1_AHBBUSWAIT_SHIFT)

/* Module Control Register 2 */
#define FSPI_MCR2_RESUMEWAIT_SHIFT	24
#define FSPI_MCR2_RESUMEWAIT_MASK	(0xFF << FSPI_MCR2_RESUMEWAIT_SHIFT)
#define FSPI_MCR2_CLKPHASERST_SHIFT	20
#define FSPI_MCR2_CLKPHASERST_MASK	(1 << FSPI_MCR2_CLKPHASERST_SHIFT)
#define FSPI_MCR2_SCKBDIFFOPT_SHIFT	19
#define FSPI_MC2_SCKBDIFFOPT_MASK	(1 << FSPI_MCR2_SCKBDIFFOPT_SHIFT)
#define FSPI_MCR2_RXDELAYOPT_SHIFT	17
#define FSPI_MCR2_RXDELAYOPT_MASK	(3 << FSPI_MCR2_RXDELAYOPT_SHIFT)
#define FSPI_MCR2_FLASHDQSOPT_SHIFT	16
#define FSPI_MCR2_FLASHDQSOPT_MASK	(1 << FSPI_MCR2_FLASHDQSOPT_SHIFT)
#define FSPI_MCR2_SAMEDEVICEEN_SHIFT	15
#define FSPI_MCR2_SAMEDEVICEEN_MASK	(1 << FSPI_MCR2_SAMEDEVICEEN_SHIFT)
#define FSPI_MCR2_CLRLEARNPHASE_SHIFT	14
#define FSPI_MCR2_CLRLEARNPHASE_MASK	(1 << FSPI_MCR2_CLRLEARNPHASE_SHIFT)
#define FSPI_MCR2_TSTMD_SHIFT		13
#define FSPI_MCR2_TSTMD_MASK		(1 << FSPI_MCR2_TSTMD_SHIFT)
#define FSPI_MCR2_SCK2OPT_SHIFT		12
#define FSPI_MCR2_SCK2OPT_MASK		(1 << FSPI_MCR2_SCK2OPT_SHIFT)
#define FSPI_MCR2_CLRAHBBUFOPT_SHIFT	11
#define FSPI_MCR2_CLRAHBBUFOPT_MASK	(1 << FSPI_MCR2_CLRAHBBUFOPT_SHIFT)
#define FSPI_MCR2_ABORTONDATSZEN_SHIFT	8
#define FSPI_MCR2_ABORTONDATSZEN_MASK	(1 << FSPI_MCR2_ABORTONDATSZEN_SHIFT)
#define FSPI_MCR2_ABORTONLEARNEN_SHIFT	7
#define FSPI_MCR2_ABORTONLEARNEN_MASK	(1 << FSPI_MCR2_ABORTONLEARNEN_SHIFT)
#define FSPI_MCR2_ABORTONREADEN_SHIFT	6
#define FSPI_MCR2_ABORTONREADEN_MASK	(1 << FSPI_MCR2_ABORTONREADEN_SHIFT)
#define FSPI_MCR2_ABORTONWRITEEN_SHIFT	5
#define FSPI_MCR2_ABORTONWRITEEN_MASK	(1 << FSPI_MCR2_ABORTONWRITEEN_SHIFT)
#define FSPI_MCR2_ABORTONDUMMYEN_SHIFT	4
#define FSPI_MCR2_ABORTONDUMMYEN_MASK	(1 << FSPI_MCR2_ABORTONDUMMYEN_SHIFT)
#define FSPI_MCR2_ABORTONMODEEN_SHIFT	3
#define FSPI_MCR2_ABORTONMODEEN_MASK	(1 << FSPI_MCR2_ABORTONMODEEN_SHIFT)
#define FSPI_MCR2_ABORTONCADDREN_SHIFT	2
#define FSPI_MCR2_ABORTONCADDREN_MASK	(1 << FSPI_MCR2_ABORTONCADDREN_SHIFT)
#define FSPI_MCR2_ABORTONRADDREN_SHIFT	1
#define FSPI_MCR2_ABORTONRADDREN_MASK	(1 << FSPI_MCR2_ABORTONRADDREN_SHIFT)
#define FSPI_MCR2_ABORTONCMDEN_SHIFT	0
#define FSPI_MCR2_ABORTONCMDEN_MASK	(1 << FSPI_MCR2_ABORTONCMDEN_SHIFT)

/* AHB Bus Control Register */
#define FSPI_AHBCR_AFLASHBASE_SHIFT	28
#define FSPI_AHBCR_AFLASHBASE_MASK	(0xF << FSPI_AHBCR_AFLASHBASE_SHIFT)
#define FSPI_AHBCR_READADDROPT_SHIFT	6
#define FSPI_AHBCR_READADDROPT_MASK	(1 << FSPI_AHBCR_READADDROPT_SHIFT)
#define FSPI_AHBCR_PREFETCHEN_SHIFT	5
#define FSPI_AHBCR_PREFETCHEN_MASK	(1 << FSPI_AHBCR_PREFETCHEN_SHIFT)
#define FSPI_AHBCR_BUFFERABLEEN_SHIFT	4
#define FSPI_AHBCR_BUFFERABLEEN_MASK	(1 << FSPI_AHBCR_BUFFERABLEEN_SHIFT)
#define FSPI_AHBCR_CACHABLEEN_SHIFT	3
#define FSPI_AHBCR_CACHABLEEN_MASK	(1 << FSPI_AHBCR_CACHABLEEN_SHIFT)
#define FSPI_AHBCR_CLRAHBTXBUF_SHIFT	2
#define FSPI_AHBCR_CLRAHBTXBUF_MASK	(1 << FSPI_AHBCR_CLRAHBTXBUF_SHIFT)
#define FSPI_AHBCR_CLRAHBRXBUF_SHIFT	1
#define FSPI_AHBCR_CLRAHBRXBUF_MASK	(1 << FSPI_AHBCR_CLRAHBRXBUF_SHIFT)
#define FSPI_AHBCR_APAREN_SHIFT		0
#define FSPI_AHBCR_APAREN_MASK		(1 << FSPI_AHBCR_APAREN_SHIFT)

/* Interrupt Enable Register */
#define FSPI_INTEN_SEQTIMEOUTEN_SHIFT	11
#define FSPI_INTEN_SEQTIMEOUTEN_MASK	(1 << FSPI_INTEN_SEQTIMEOUTEN_SHIFT)
#define FSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT 10
#define FSPI_INTEN_AHBBUSTIMEOUTEN_MASK (1 << FSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)
#define FSPI_INTEN_SCKSTOPBYWREN_SHIFT 9
#define FSPI_INTEN_SCKSTOPBYWREN_MASK	(1 << FSPI_INTEN_SCKSTOPBYWREN_SHIFT)
#define FSPI_INTEN_SCKSTOPBYRDEN_SHIFT	8
#define FSPI_INTEN_SCKSTOPBYRDEN_MASK	(1 << FSPI_INTEN_SCKSTOPBYRDEN_SHIFT)
#define FSPI_INTEN_DATALEARNFAILEN_SHIFT 7
#define FSPI_INTEN_DATALEARNFAILEN_MASK	(1 << FSPI_INTEN_DATALEARNFAILEN_SHIFT)
#define FSPI_INTEN_IPTXWEEN_SHIFT	6
#define FSPI_INTEN_IPTXWEEN_MASK	(1 << FSPI_INTEN_IPTXWEEN_SHIFT)
#define FSPI_INTEN_IPRXWAEN_SHIFT	5
#define FSPI_INTEN_IPRXWAEN_MASK	(1 << FSPI_INTEN_IPRXWAEN_SHIFT)
#define FSPI_INTEN_AHBCMDERREN_SHIFT	4
#define FSPI_INTEN_AHBCMDERREN_MASK	(1 << FSPI_INTEN_AHBCMDERREN_SHIFT)
#define FSPI_INTEN_IPCMDERREN_SHIFT	3
#define FSPI_INTEN_IPCMDERREN_MASK	(1 << FSPI_INTEN_IPCMDERREN_SHIFT)
#define FSPI_INTEN_AHBCMDGEEN_SHIFT	2
#define FSPI_INTEN_AHBCMDGEEN_MASK	(1 << FSPI_INTEN_AHBCMDGEEN_SHIFT)
#define FSPI_INTEN_IPCMDGEEN_SHIFT	1
#define FSPI_INTEN_IPCMDGEEN_MASK	(1 << FSPI_INTEN_IPCMDGEEN_SHIFT)
#define FSPI_INTEN_IPCMDDONEEN_SHIFT	0
#define FSPI_INTEN_IPCMDDONEEN_MASK	(1 << FSPI_INTEN_IPCMDDONEEN_SHIFT)

/* Interrupt Register */
#define FSPI_INTR_SEQTIMEOUT_SHIFT	11
#define FSPI_INTR_SEQTIMEOUT_MASK	(1 << FSPI_INTR_SEQTIMEOUT_SHIFT)
#define FSPI_INTR_AHBBUSTIMEOUT_SHIFT	10
#define FSPI_INTR_AHBBUSTIMEOUT_MASK	(1 << FSPI_INTR_AHBBUSTIMEOUT_SHIFT)
#define FSPI_INTR_SCKSTOPBYWR_SHIFT	9
#define FSPI_INTR_SCKSTOPBYWR_MASK	(1 << FSPI_INTR_SCKSTOPBYWR_SHIFT)
#define FSPI_INTR_SCKSTOPBYRD_SHIFT	8
#define FSPI_INTR_SCKSTOPBYRD_MASK	(1 << FSPI_INTR_SCKSTOPBYRD_SHIFT)
#define FSPI_INTR_DATALEARNFAIL_SHIFT	7
#define FSPI_INTR_DATALEARNFAIL_MASK	(1 << FSPI_INTR_DATALEARNFAIL_SHIFT)
#define FSPI_INTR_IPTXWE_SHIFT		6
#define FSPI_INTR_IPTXWE_MASK		(1 << FSPI_INTR_IPTXWE_SHIFT)
#define FSPI_INTR_IPRXWA_SHIFT		5
#define FSPI_INTR_IPRXWA_MASK		(1 << FSPI_INTR_IPRXWA_SHIFT)
#define FSPI_INTR_AHBCMDERR_SHIFT	4
#define FSPI_INTR_AHBCMDERR_MASK	(1 << FSPI_INTR_AHBCMDERR_SHIFT)
#define FSPI_INTR_IPCMDERR_SHIFT	3
#define FSPI_INTR_IPCMDERR_MASK		(1 << FSPI_INTR_IPCMDERR_SHIFT)
#define FSPI_INTR_AHBCMDGE_SHIFT	2
#define FSPI_INTR_AHBCMDGE_MASK		(1 << FSPI_INTR_AHBCMDGE_SHIFT)
#define FSPI_INTR_IPCMDGE_SHIFT		1
#define FSPI_INTR_IPCMDGE_MASK		(1 << FSPI_INTR_IPCMDGE_SHIFT)
#define FSPI_INTR_IPCMDDONE_SHIFT	0
#define FSPI_INTR_IPCMDDONE_MASK	(1 << FSPI_INTR_IPCMDDONE_SHIFT)

/* AHB RX Buffer 0-7 Control Register 0 */
#define FSPI_AHBBUFXCR0_PREFETCHEN_SHIFT 31
#define FSPI_AHBBUFXCR0_PREFETCHEN_MASK (1 << FSPI_AHBBUFXCR0_PREFETCHEN_SHIFT)
#define FSPI_AHBBUFXCR0_PRIORITY_SHIFT	24
#define FSPI_AHBBUFXCR0_PRIORITY_MASK	(7 << FSPI_AHBBUFXCR0_PRIORITY_SHIFT)
#define FSPI_AHBBUFXCR0_MSTRID_SHIFT	16
#define FSPI_AHBBUFXCR0_MSTRID_MASK	(0xF << FSPI_AHBBUFXCR0_MSTRID_SHIFT)
#define FSPI_AHBBUFXCR0_BUFSZ_SHIFT	0
#define FSPI_AHBBUFXCR0_BUFSZ_MASK	(0xFF << FSPI_AHBBUFXCR0_BUFSZ_SHIFT)

/* Flash A1/A2/B1/B2 Control 0 */
#define FSPI_FLSHXCR0_FLSHSZ_SHIFT	0
#define FSPI_FLSHXCR0_FLSHSZ_MASK	(0x7FFFFF << FSPI_FLSHXCR0_SZ_SHIFT)

/* Flash A1/A2/B1/B2 Control 1 */
#define FSPI_FLSHXCR1_CSINTERVAL_SHIFT	16
#define FSPI_FLSHXCR1_CSINTERVAL_MASK \
	(0xFFFF << FSPI_FLSHXCR1_CSINTERVAL_SHIFT)
#define FSPI_FLSHXCR1_CSINTERVALUNIT_SHIFT 15
#define FSPI_FLSHXCR1_CSINTERVALUNIT_MASK \
	(1 << FSPI_FLSHXCR1_CSINTERVALUNIT_SHIFT)
#define FSPI_FLSHXCR1_CAS_SHIFT		11
#define FSPI_FLSHXCR1_CAS_MASK		(0xF << FSPI_FLSHXCR0_CAS_SHIFT)
#define FSPI_FLSHXCR1_WA_SHIFT		10
#define FSPI_FLSHXCR1_WA_MASK		(1 << FSPI_FLSHXCR0_WA_SHIFT)
#define FSPI_FLSHXCR1_TCSH_SHIFT	5
#define FSPI_FLSHXCR1_TCSH_MASK		(0x1F << FSPI_FLSHXCR0_TCSH_SHIFT)
#define FSPI_FLSHXCR1_TCSS_SHIFT	0
#define FSPI_FLSHXCR1_TCSS_MASK		(0x1F << FSPI_FLSHXCR0_TCSS_SHIFT)

/* Flash A1/A2/B1/B2 Control 2 */
#define FSPI_FLSHXCR2_CLRINSTRPTR_SHIFT	31
#define FSPI_FLSHXCR2_CLRINSTRPTR_MASK	(1 << FSPI_FLSHXCR2_CLRINSTRPTR_SHIFT)
#define FSPI_FLSHXCR2_AWRWAITUNIT_SHIFT	28
#define FSPI_FLSHXCR2_AWRWAITUNIT_MASK	(0x7 << FSPI_FLSHXCR2_AWRWAITUNIT_SHIFT)
#define FSPI_FLSHXCR2_AWRWAIT_SHIFT	16
#define FSPI_FLSHXCR2_AWRWAIT_MASK	(0xFFF << FSPI_FLSHXCR2_AWRWAIT_SHIFT)
#define FSPI_FLSHXCR2_AWRSEQNUM_SHIFT	13
#define FSPI_FLSHXCR2_AWRSEQNUM_MASK	(0x7 << FSPI_FLSHXCR2_AWRSEQNUM_SHIFT)
#define FSPI_FLSHXCR2_AWRSEQID_SHIFT	8
#define FSPI_FLSHXCR2_AWRSEQID_MASK	(0x1F << FSPI_FLSHXCR2_AWRSEQID_SHIFT)
#define FSPI_FLSHXCR2_ARDSEQNUM_SHIFT	5
#define FSPI_FLSHXCR2_ARDSEQNUM_MASK	(0x7 << FSPI_FLSHXCR2_ARDSEQN_SHIFT)
#define FSPI_FLSHXCR2_ARDSEQID_SHIFT	0
#define FSPI_FLSHXCR2_ARDSEQID_MASK	(0x1F << FSPI_FLSHXCR2_ARDSEQID_SHIFT)

/* Flash Control Register 3 */
#define FSPI_FLSHCR3_SIOOENONIDLE_SHIFT 24
#define FSPI_FLSHCR3_SIOOENONIDLE_MASK (0xff << FSPI_FLSHCR3_SIOOENONIDLE_SHIFT)
#define FSPI_FLSHCR3_SIOOEIDLE_SHIFT	16
#define FSPI_FLSHCR3_SIOOEIDLE_MASK	(0xff << FSPI_FLSHCR3_SIOOEIDLE_SHIFT)
#define FSPI_FLSHCR3_SIODONONIDLE_SHIFT	8
#define FSPI_FLSHCR3_SIODONONIDLE_MASK \
	(0xff << FSPI_FLSHCR3_SIODONONIDLE_SHIFT)
#define FSPI_FLSHCR3_SIODOIDLE_SHIFT	0
#define FSPI_FLSHCR3_SIODOIDLE_MASK	(0xff << FSPI_FLSHCR3_SIODOIDLE_SHIFT)

/* Flash Control Register 4  */
#define FSPI_FLSHCR4_WMOPT_SHIFT	0
#define FSPI_FLSHCR4_WMOPT_MASK		(1 << FSPI_FLSHCR4_WMOPT_SHIFT)

/* IP Control Register 0 */

/* IP Control Register 1 */
#define FSPI_IPCR1_IPAREN_SHIFT		31
#define FSPI_IPCR1_IPAREN_MASK		(1 << FSPI_IPCR1_IPAREN_SHIFT)
#define FSPI_IPCR1_ISEQNUM_SHIFT	24
#define FSPI_IPCR1_ISEQNUM_MASK		(0x7 << FSPI_IPCR1_ISEQNUM_SHIFT)
#define FSPI_IPCR1_ISEQID_SHIFT		16
#define FSPI_IPCR1_ISEQID_MASK		(0x1F << FSPI_IPCR1_ISEQID_SHIFT)
#define FSPI_IPCR1_IDATSZ_SHIFT		0
#define FSPI_IPCR1_IDATSZ_MASK		(0xFFFF << FSPI_IPCR1_IDATSZ_SHIFT)

/* IP Command Register */
#define FSPI_IPCMD_TRG_SHIFT		0
#define FSPI_IPCMD_TRG_MASK		(1 << FSPI_IPCMD_TRG_SHIFT)


/* IP RX FIFO Control Register */
#define FSPI_IPRXFCR_RXWMRK_SHIFT	2
#define FSPI_IPRXFCR_RXWMRK_MASK	(0x3F << FSPI_IPRXFCR_RXWMRK_SHIFT)
#define FSPI_IPRXFCR_RXDMAEN_SHIFT	1
#define FSPI_IPRXFCR_RXDMAEN_MASK	(1 << FSPI_IPRXFCR_RXDMAEN_SHIFT)
#define FSPI_IPRXFCR_CLRIPRXF_SHIFT	0
#define FSPI_IPRXFCR_CLRIPRXF_MASK	(1 << FSPI_IPRXFCR_CLRIPRXF_SHIFT)

/* IP TX FIFO Control Register */
#define FSPI_IPTXFCR_TXWMRK_SHIFT	2
#define FSPI_IPTXFCR_TXWMRK_MASK	(0x7F << FSPI_IPTXFCR_TXWMRK_SHIFT)
#define FSPI_IPTXFCR_TXDMAEN_SHIFT	1
#define FSPI_IPTXFCR_TXDMAEN_MASK	(1 << FSPI_IPTXFCR_TXDMAEN_SHIFT)
#define FSPI_IPTXFCR_CLRIPTXF_SHIFT	0
#define FSPI_IPTXFCR_CLRIPTXF_MASK	(1 << FSPI_IPTXFCR_CLRIPTXF_SHIFT)

/*Status Register 0*/
#define FSPI_STS0_DATALEARNPHASEB_SHIFT	8
#define FSPI_STS0_DATALEARNPHASEB_MASK	(0xF << FSPI_STS0_DATALEARNPHASEB_SHIFT)
#define FSPI_STS0_DATALEARNPHASEA_SHIFT	4
#define FSPI_STS0_DATALEARNPHASEA_MASK	(0xF << FSPI_STS0_DATALEARNPHASEA_SHIFT)
#define FSPI_STS0_ARBCMDSRC_SHIFT	2
#define FSPI_STS0_ARBCMDSRC_MASK	(3 << FSPI_STS0_ARBCMDSRC_SHIFT)
#define FSPI_STS0_ARBIDLE_SHIFT		1
#define FSPI_STS0_ARBIDLE_MASK		(1 << FSPI_STS0_ARBIDLE_SHIFT)
#define FSPI_STS0_SEQIDLE_SHIFT		0
#define FSPI_STS0_SEQIDLE_MASK		(1 << FSPI_STS0_SEQIDLE_SHIFT)

/* Status Register 1 */
#define FSPI_STS1_IPCMDERRCODE_SHIFT	24
#define FSPI_STS1_IPCMDERRCODE_MASK	(0xF << FSPI_STS1_IP_ERRCD_SHIFT)
#define FSPI_STS1_IPCMDERRID_SHIFT	16
#define FSPI_STS1_IPCMDERRID_MASK	(0x1F << FSPI_STS1_IPCMDERRID_SHIFT)
#define FSPI_STS1_AHBCMDERRCODE_SHIFT	8
#define FSPI_STS1_AHBCMDERRCODE_MASK	(0xF << FSPI_STS1_AHBCMDERRCODE_SHIFT)
#define FSPI_STS1_AHBCMDERRID_SHIFT	0
#define FSPI_STS1_AHBCMDERRID_MASK	(0x1F << FSPI_STS1_AHBCMDERRID_SHIFT)

/* AHB Suspend Status Register */
#define FSPI_AHBSPNST_DATLFT_SHIFT	16
#define FSPI_AHBSPNST_DATLFT_MASK	(0xFFFF << FSPI_AHBSPNST_DATLFT_SHIFT)
#define FSPI_AHBSPNST_BUFID_SHIFT	1
#define FSPI_AHBSPNST_BUFID_MASK	(7 << FSPI_AHBSPNST_BUFID_SHIFT)
#define FSPI_AHBSPNST_ACTIVE_SHIFT	0
#define FSPI_AHBSPNST_ACTIVE_MASK	(1 << FSPI_AHBSPNST_ACTIVE_SHIFT)

/* IP RX FIFO Status Register */
#define FSPI_IPRXFSTS_RDCNTR_SHIFT	16
#define FSPI_IPRXFSTS_RDCNTR_MASK	(0xFFFF << FSPI_IPRXFSTS_RDCNTR_SHIFT)
#define FSPI_IPRXFSTS_FILL_SHIFT	0
#define FSPI_IPRXFSTS_FILL_MASK		(0xFF << FSPI_IPRXFSTS_FILL_SHIFT)

/* IP TX FIFO Status Register */
#define FSPI_IPTXFSTS_WRCNTR_SHIFT	16
#define FSPI_IPTXFSTS_WRCNTR_MASK	(0xFFFF << FSPI_IPTXFSTS_WRCNTR_SHIFT)
#define FSPI_IPTXFSTS_FILL_SHIFT	0
#define FSPI_IPTXFSTS_FILL_MASK		(0xFF << FSPI_IPTXFSTS_FILL_SHIFT)

/*LUT Keys*/

#define FSPI_LUTKEY_VALUE		0x5AF05AF0

/* LUT Control Register */
#define FSPI_LUTCR_LOCK			0x1
#define FSPI_LUTCR_UNLOCK		0x2

/* register map end */

#define OPRND0_SHIFT			0
#define OPRND0(x)			((x) << OPRND0_SHIFT)
#define PAD0_SHIFT			8
#define PAD0(x)				((x) << PAD0_SHIFT)
#define INSTR0_SHIFT			10
#define INSTR0(x)			((x) << INSTR0_SHIFT)
#define OPRND1_SHIFT			16
#define OPRND1(x)			((x) << OPRND1_SHIFT)
#define PAD1_SHIFT			24
#define PAD1(x)				((x) << PAD1_SHIFT)
#define INSTR1_SHIFT			26
#define INSTR1(x)			((x) << INSTR1_SHIFT)

#define LUT_STOP		0x00
#define LUT_CMD			0x01
#define LUT_ADDR		0x02
#define LUT_CADDR_SDR		0x03
#define LUT_MODE		0x04
#define LUT_MODE2		0x05
#define LUT_MODE4		0x06
#define LUT_MODE8		0x07
#define LUT_WRITE		0x08
#define LUT_READ		0x09
#define LUT_LEARN_SDR		0x0A
#define LUT_DATSZ_SDR		0x0B
#define LUT_DUMMY		0x0C
#define LUT_DUMMY_RWDS_SDR	0x0D
#define LUT_JMP_ON_CS		0x1F
#define LUT_CMD_DDR		0x21
#define LUT_ADDR_DDR		0x22
#define LUT_CADDR_DDR		0x23
#define LUT_MODE_DDR		0x24
#define LUT_MODE2_DDR		0x25
#define LUT_MODE4_DDR		0x26
#define LUT_MODE8_DDR		0x27
#define LUT_WRITE_DDR		0x28
#define LUT_READ_DDR		0x29
#define LUT_LEARN_DDR		0x2A
#define LUT_DATSZ_DDR		0x2B
#define LUT_DUMMY_DDR		0x2C
#define LUT_DUMMY_RWDS_DDR	0x2D

#define LUT_PAD1		0
#define LUT_PAD2		1
#define LUT_PAD4		2
#define LUT_PAD8		3

#define ADDR8BIT		0x08
#define ADDR16BIT		0x10
#define ADDR24BIT		0x18
#define ADDR32BIT		0x20

#endif /* _NXP_FSPI_H_ */
